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大学University · イタリアItaly · 2022–2026 LIVE

University of Bologna

世界World 25位 (0 pt) · 対象論文Papers 14

年別の推移Papers per year

会議・論文誌別の論文数（フルカウント）Papers per venue (full count)

012342022 JSSC: 12022 ESSERC: 2320222023 ISSCC: 12023 ESSERC: 1220232024 VLSI: 12024 JSSC: 22024 ESSERC: 1420242025 JSSC: 12025 ESSERC: 1220252026 JSSC: 22026 CICC: 132026
ISSCCVLSIJSSCCICCESSERC
数値表を表示Show table
会議・論文誌Venue20222023202420252026
ISSCC–1–––
VLSI––1––
JSSC1–212
CICC––––1
ESSERC2111–

会議・論文誌別By venue

順位はフルカウントでの値です。Ranks use the full count.

会議・論文誌VenueフルFull 筆頭First按分Frac. 順位Rank
ISSCC Tier 1110.41世界World #112
VLSI Tier 1100.14世界World #78
JSSC Tier 1632.06世界World #76
CICC Tier 2110.75世界World #113
A-SSCC Tier 2000.00–
ESSERC Tier 2522.23世界World #32

対象論文Papers

太字はこの機関の所属として確認できた著者です。Bold: authors affiliated with this institution.

  1. CICC
    2026
    A Low-Power 1.2 TFLOPS/W Merge-Split RVV Processor for Mixed Scalar-Vector Workloads
    DOI
    Mattia Sinigaglia, Marco Bertuletti, Gianmarco Ottavi, Amirhossein Kiamarzi, Matteo Perotti, Giuseppe Tagliavini, Luca Benini, Davide Rossi
    University of Bologna · Integrated Systems Laboratory
  2. JSSC
    2026
    A 28-nm FD-SOI CMOS Analog-IMC Core Based on PCM Featuring 8 512 × 512-Weight Layers and 28M Weights×TOPs/W/mm 2
    DOI
    Marco Pasotti, Riccardo Zurla, J. J. Bertolini Agnoletto, Emanuela Calvetti, Alessio Antolini, Andrea Lico, Giuseppe Desoli, Riccardo Vignali, Luca Iannelli, Luigi Croce, Francesco Zavalloni, Eleonora Franchi Scarselli, Alessandro Cabrini
    STMicroelectronics · University of Bologna · University of Pavia
  3. JSSC
    2026
    High-Precision Close-to-Analog Programming of PCM Cells as Devices for AiMC Edge-AI
    DOI
    Alessio Antolini, Andrea Lico, Francesco Zavalloni, Lorenzo Greco, Riccardo Zurla, Jacopo Bertolini, Riccardo Vignali, Luca Iannelli, Emanuela Calvetti, Marco Pasotti, Alessandro Cabrini, Eleonora Franchi Scarselli
    University of Bologna · STMicroelectronics · University of Pavia
  4. ESSERC
    2025
    28 M Weights $\times$ TOPs $/ \mathrm{W}/\text{mm}^{2}$ PCM-Based Analog in-Memory Computing Core with 8 $512 \times 512{}$-Weight Layers in 28 nm FD-SOI CMOS
    DOI
    M. Pasotti, R. Zurla, J. J. Bertolini Agnoletto, E. Calvetti, A. Antolini, L. Croce, G. Desoli, L. Iannelli, A. Lico, R. Vignali, F. Zavalloni, E. Franchi Scarselli, A. Cabrini
    STMicroelectronics · University of Bologna · University of Pavia
  5. JSSC
    2025
    Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12-nm FinFET
    DOI
    Paul Scheffler, Thomas Benz, Viviane Potocnik, Tim Fischer, Luca Colagrande, Nils Wistoff, Yichao Zhang, Luca Bertaccini, Gianmarco Ottavi, Manuel Eggimann, Matheus Cavalcante, Gianna Paulin, Frank K. Gürkaynak, Davide Rossi, Luca Benini
    ETH Zurich · Integrated Systems Laboratory · University of Bologna · Stanford University
  6. ESSERC
    2024
    Circuits and Systems for Embodied AI: Exploring uJ Multi-Modal Perception for Nano-UAVs on the Kraken Shield
    DOI
    Viviane Potocnik, Alfio Di Mauro, Lorenzo Lamberti, Victor Kartsch, Moritz Scherer, Francesco Conti, Luca Benini
    ETH Zurich · University of Bologna
  7. JSSC
    2024
    Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2–8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing
    DOI
    Francesco Conti, Gianna Paulin, Angelo Garofalo, Davide Rossi, Alfio Di Mauro, Georg Rutishauser, Gianmarco Ottavi, Manuel Eggiman, Hayate Okuhara, Luca Benini
    University of Bologna · ETH Zurich · Integrated Systems Laboratory · National University of Singapore
  8. JSSC
    2024
    Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality With At-MRAM Neural Engine
    DOI
    Arpan Suravi Prasad, Moritz Scherer, Francesco Conti, Davide Rossi, Alfio Di Mauro, Manuel Eggimann, Jorge Tomás Gómez, Ziyun Li, Syed Shakib Sarwar, Zhao Wang, Barbara De Salvo, Luca Benini
    ETH Zurich · Integrated Systems Laboratory · University of Bologna · Universidad de Los Andes, Chile
  9. VLSI
    2024
    Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET
    DOI
    Gianna Paulin, Paul Scheffler, Thomas Benz, Matheus Cavalcante, Tim Fischer, Manuel Eggimann, Yichao Zhang, Nils Wistoff, Luca Bertaccini, Luca Colagrande, Gianmarco Ottavi, Frank K. Gürkaynak, Davide Rossi, Luca Benini
    ETH Zurich · Stanford University · University of Bologna
  10. ESSERC
    2023
    Siracusa: A Low-Power On-Sensor RISC-V SoC for Extended Reality Visual Processing in 16nm CMOS
    DOI
    Moritz Scherer, Manuel Eggimann, Alfio Di Mauro, Arpan Suravi Prasad, Francesco Conti, Davide Rossi, Jorge Tomás Gómez, Ziyun Li, Syed Shakib Sarwar, Zhao Wang, Barbara De Salvo, Luca Benini
    ETH Zurich · University of Bologna · Meta
  11. ISSCC
    2023
    22.1 A 12.4TOPS/W @ 136GOPS AI-IoT System-on-Chip with 16 RISC-V, 2-to-8b Precision-Scalable DNN Acceleration and 30%-Boost Adaptive Body Biasing
    DOI
    Francesco Conti, Davide Rossi, Gianna Paulin, Angelo Garofalo, Alfio Di Mauro, Georg Rutishauer, Gian marco Ottavi, Manuel Eggimann, Hayate Okuhara, Vincent Huard, Olivier Montfort, Lionel Jure, Nils Exibard, Pascal Gouedo, Mathieu Louvat, Emmanuel Botte, Luca Benini
    University of Bologna · ETH Zurich · Dolphin Design (France)
  12. ESSERC
    2022
    An embedded PCM Peripheral Unit adding Analog MAC In-Memory Computing Feature addressing Non-linearity and Time Drift Compensation
    DOI
    Alessio Antolini, Andrea Lico, Eleonora Franchi Scarselli, Antonio Gnudi, Luca Perilli, Mattia Luigi Torres, Marcella Carissimi, Marco Pasotti, Roberto Antonio Canegallo
    University of Bologna · STMicroelectronics
  13. ESSERC
    2022
    Darkside: 2.6GFLOPS, 8.7mW Heterogeneous RISC-V Cluster for Extreme-Edge On-Chip DNN Inference and Training
    DOI
    Angelo Garofalo, Matteo Perotti, Luca Valente, Yvan Tortorella, Alessandro Nadalini, Luca Benini, Davide Rossi, Francesco Conti
    University of Bologna · Integrated Systems Laboratory
  14. JSSC
    2022
    Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode
    DOI
    Davide Rossi, Francesco Conti, Manuel Eggiman, Alfio Di Mauro, Giuseppe Tagliavini, Stefan Mach, Marco Guermandi, Antonio Pullini, Igor Loi, Jie Chen, Eric Flamand, Luca Benini
    University of Bologna · ETH Zurich